The present invention relates to fabrication of semiconductor integrated circuit structures. In particular, the invention relates to techniques for forming vias in multi-level interconnect integrated circuits using self-aligned copper-based via pillars and, preferably, copper as part of the upper level and lower level interconnect structure, and a conformal metal-like material, such as CVD TiN or PVD TaN, as a diffusion barrier for the copper interconnect structure.
Integrated circuits commonly use multi-level metal interconnects to reduce the layout area required for the tens or hundreds of thousands of semiconductor elements that typically form an integrated circuit structure. This reduction in layout area is possible because the metal layers used in multi-level metal schemes are separated by dielectric material that allows criss-crossing of the separated metal layers without electrical shorting. Electrical connections between metal layers are created by forming small apertures in the dielectric material and filling the apertures with a conducting material, e.g. aluminum. These connections, usually made between consecutive metal layers, are known as xe2x80x9cvias.xe2x80x9d
As semiconductor device geometries continue to shrink into the submicron range, it is increasingly difficult to maintain planar metal and dielectric surfaces during the formation of multi-level metal interconnect structures. This lack of planarity can cause several problems. For example, if the underlying topography coated by a photoresist layer contains abrupt steps, then the thickness of the photoresist layer will not be uniform. This can occur, for example, when the photoresist is applied over features formed earlier in a semiconductor device process that protrude from the surface of the structure. The resulting non-uniformity in the photoresist thickness can lead to some regions of the patterned photoresist layer being insufficiently thick to protect underlying features during a later etching step and other regions being excessively thick so that the full thickness of the photoresist layer cannot be exposed due to the depth-of-focus limitations of photolithography at sub-micron dimensions. Also, poor planarity of metal and dielectric layers promotes poor metal step coverage which increases metal sheet-resistance, susceptibility to current-stress failure, electromigration problems and the probability of electrical opens. In addition, poor planarity in underlying metal or dielectric layers formed earlier in a semiconductor device process further increases the difficulty of establishing planarity in overlying metal or dielectric layers formed later in the process.
Another difficulty associated with via formation for multi-level metal interconnect structures in sub-micron architectures is the alignment of upper and lower metal layers with a via aperture formed in an intermediate dielectric. This alignment is difficult to achieve because of the small distance between device features in sub-micron devices and, thus, the reduced tolerance available for alignment errors. Misalignment of a via relative to connected upper and lower metal layers can lead to reduced device yield, increased via resistance and poor metal coverage in the via. For example, in a standard via, misalignment of the via relative to the lower metal layer results in overetching into the dielectric underlying the lower metal layer, thereby increasing the aspect ratio of the via opening and preventing adequate step coverage when the via is later filled with metal. The result is a poor contact interface in the via and increased via resistance. Misalignment of an upper metal layer relative to a via results in overetching, or notching, of the lower metal layer. The notched lower metal layer exhibits increased current density and is, thus, more susceptible to failure from electromigration or current stress.
In many semiconductor devices, the layout dimensions of upper and lower metal layers connecting to vias are extended in the vicinity of the via to form a layout frame, or head, around the via. This is known as xe2x80x9cframingxe2x80x9d the via. The frame provides additional alignment margin such that if partial misalignment of an upper and lower metal layer relative to the intended via location occurs, the actual formed via will still overlie a portion of a lower metal layer or underlie a portion of an upper metal layer. However, an adverse effect of using framed vias in a semiconductor device layout is that the packing density is substantially decreased (or the layout area is substantially increased).
A third difficulty associated with via formation for multi-level metal interconnects in sub-micron architectures is the contact resistance of the vias caused by polymer residue formation during the etching of the vias. These residues are typically formed during plasma etching and may contaminate the bottom of the via, causing a poor metallurgical contact between the lower metal layer and the metal in the via.
Accordingly, a need exists for a method of forming a via for connecting multi-level metal interconnects in sub-micron semiconductor device architectures that improves the surface planarity of formed metal and dielectric layers, reduces problems associated with via misalignment, reduces contact resistance problems associated with polymer residues, and lowers associated manufacturing costs.
Commonly-assigned and co-pending Application Ser. No. 09/295,898, U.S. Pat. No. 6,103,629 filed on the same date as this application, titled xe2x80x9cSelf-Aligned Interconnect Using High Selectivity Metal Pillars and a Via Exclusion Maskxe2x80x9d, discloses techniques for forming vias in multi-level metal ICs using self-aligned metal via pillars between interconnect levels. The metal via pillars include an upper surface that exhibits high selectivity in the etch of the upper metal interconnect layer.
As new integrated circuit manufacturing technologies emerge, it has become possible to use copper, instead of, for example, aluminum, in commercial metal interconnect structures.
Commonly-assigned and co-pending Application Ser. No. 09/295,838, U.S. Pat. No. 6,140,238 filed on the same date as this application, titled xe2x80x9cSelf-Aligned Copper Interconnect Structure and Method of Manufacturing Samexe2x80x9d, discloses an interconnect structure that, in its preferred embodiment, provides copper-based lower and upper patterned interconnect layers that are separated by dielectric and connected by via pillars, also copper-based, that extend through the dielectric. A layer of silicon oxynitride (SiON) serves as a copper diffusion barrier layer.
The present invention provides self-aligned vias in a copper-based multi-level interconnect structure using a conformal metal-like material, such as CVD TiN or PVD TaN, as a copper diffusion barrier.
In accordance with a preferred embodiment of the invention, the lower conductive interconnect layer includes a diffusion barrier layer, a first copper-based layer formed on the diffusion barrier layer, and an etch stop layer formed on the copper-based layer. A second copper-based layer is formed on the etch stop layer and an optional conductive antireflective diffusion barrier layer is formed on the second copper-based layer. The upper antireflective diffusion barrier layer is then patterned and etched and utilized as a conventional hardmask to etch the second copper-based layer, the etch stop layer, the first copper-based layer and the lower diffusion barrier layer to define a patterned metal stack. A thin layer of conformal metal-like material, e.g. CVD TiN or PVD TaN, having good barrier properties against copper diffusion is then deposited over the patterned stack. An anisotropic spacer etchback of the conformal conductive barrier material is then performed such that barrier material is removed from horizontal surfaces, leaving conductive diffusion barrier material on vertical sidewalls of the patterned stack. A first dielectric material is then deposited, filling the gaps between the patterned stack. The structure is then planarized, e.g. using chemical mechanical polishing (CMP), leaving the upper surface of the patterned antireflective diffusion barrier layer exposed. The exposed antireflective diffusion barrier layer is then masked and etched to define copper-based via pillars that have caps formed of the conductive antireflective material. The etch stop layer serves as an etch stop to the copper etch. If the copper via pillar etch is selective to the conductive barrier material, then, to avoid shorts between via pillars, the via pillar etch must be followed by an isotropic etch of the exposed conductive barrier material that is selective to copper. If the copper via pillar etch is not selective to the conductive barrier material, then exposed conductive barrier material will be removed by the copper etch and the process can proceed. Since the conductive diffusion barrier material has now been removed wherever it was exposed by the copper etch, and since the exposed sidewalls of the via pillars are thus not now protected by a diffusion barrier, a layer of conformal diffusion barrier dielectric material, e.g. silicon nitride, is deposited over exposed surfaces. Following deposition of the conformal diffusion barrier dielectric material, the gaps between the via pillars are filled with dielectric material. The dielectric material is then planarized to expose the upper surface of the antireflective diffusion barrier material that caps the via pillars. An upper conductive layer is then formed in electrical contact with the exposed pillar caps. The upper conductive layer comprises a material having high selectivity to the material of the antireflective/diffusion barrier layer. Therefore, etching of the upper conductive layer during its patterning will not etch the underlying via pillars in the event of mask misalignment.
If an antireflective layer is not utilized on the copper via pillar layer, then a conventional hardmask, e.g. thick silicon dioxide, is used to pattern the metal stack. A hardmask is needed because a conventional photoresist mask will not survive the high temperatures needed to etch copper.
Use of a conformal metal-like diffusion barrier material, such as CVD TiN or PVD TaN, improves over use of other copper barrier diffusion materials, such as SiON. SiON has a higher dielectric constant than oxide, so RC time delay and intralayer metal capacitance is improved because there is no SiON. Because insulator material SiON is replaced with a conductor, lower resistivity, improved current flow and, thus, improved device speed, are obtained.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.